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MRF89XA
5.3
Switching Times and Procedures
As an ultra low-power device, the MRF89XA can be
configured for low minimum average power consump-
tion. To minimize consumption the following optimized
transitions between modes are shown.
5.3.1
OPTIMIZED RECEIVE CYCLE
The lowest-power RX cycle is shown in Figure 5-1 .
FIGURE 5-1:
MRF89XA
IDD
IDDRX
3.0 mA typ.
IDDFS
1.3 mA typ.
IDDST
65 μA typ.
IDDSL
100 nA typ.
OPTIMIZED RX CYCLE
RX
Time
MRF89XA can be put in
Any other mode
Wait
TSWRF
Receiver is ready:
- RSSI sampling is valid after a 1/ f dev period
- Received data is valid
Wait
TSFS
Set MRF89XA in RX mode
Wait for Receiver settling
Wait
TSOSC
Set MRF89XA in FS mode
Wait for PLL settling
Set MRF89XA in Stand-by mode
Wait for XO settling
Note
1:
If the lock detect indicator is available on an external interrupt pin of the companion microcontroller, it can be used to optimize
TSFS, without having to wait the maximum specified TSFS.
DS70622C-page 108
Preliminary
? 2010–2011 Microchip Technology Inc.
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